The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7739571 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 15, 2010

Filed:

Sep. 27, 2005
Applicants:

Yasuteru Maeda, Kyoto, JP;

Toshinori Maeda, Osaka, JP;

Inventors:

Yasuteru Maeda, Kyoto, JP;

Toshinori Maeda, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/27 (2006.01); G06F 11/25 (2006.01); G06F 11/263 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor integrated circuit, there is constructed a test expected value programming circuithaving an input/input-output padfor retrieving a ground/power-source signalfrom a ground terminalor a power source terminalconnected to the semiconductor integrated circuit, a switchfor selectively switching the outputting of the ground/power-source signalinputted via the input/input-output pad, and an expected value generation circuitfor generating a test expected value signalbased on a switch output signaloutputted from the switch


Find Patent Forward Citations

Maeda, Yasuteru. (2010). Semiconductor integrated circuit and system lsi having a test expected value programming circuit (U.S. Patent No. 7739571). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7739571

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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