The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Sep. 05, 2008
Applicants:
Puneet Sareen, Freising, DE;
Hermann Seibold, Haag, DE;
Inventors:
Puneet Sareen, Freising, DE;
Hermann Seibold, Haag, DE;
Assignee:
Texas Instruments Deutschland GmbH, Freising, DE;
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/16 (2006.01);
U.S. Cl.
CPC ...
Abstract
In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.