Current-voltage-based method for evaluating thin dielectrics based on interface traps

Abstract

A method for evaluating gate dielectrics () includes providing a test structure (). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing () is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed () including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed () wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated () from the pre-stress and post-stress I-V test data.