The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
May. 15, 2007
Wataru Saito, Kanagawa-ken, JP;
Syotaro Ono, Kanagawa-ken, JP;
Masakatsu Takashita, Kanagawa-ken, JP;
Yasuto Sumi, Kanagawa-ken, JP;
Masaru Izumisawa, Kanagawa-ken, JP;
Hiroshi Ohta, Tokyo, JP;
Wataru Sekine, Tokyo, JP;
Wataru Saito, Kanagawa-ken, JP;
Syotaro Ono, Kanagawa-ken, JP;
Masakatsu Takashita, Kanagawa-ken, JP;
Yasuto Sumi, Kanagawa-ken, JP;
Masaru Izumisawa, Kanagawa-ken, JP;
Hiroshi Ohta, Tokyo, JP;
Wataru Sekine, Tokyo, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.