The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

Feb. 27, 2007
Applicants:

Puneet Kohli, Austin, TX (US);

Craig Huffman, Krugerville, TX (US);

Manfred Ramin, Austin, TX (US);

Inventors:

Puneet Kohli, Austin, TX (US);

Craig Huffman, Krugerville, TX (US);

Manfred Ramin, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
Abstract

A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate.


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