The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

Dec. 28, 2006
Applicants:

Cha Deok Dong, Icheon-si, KR;

Whee Won Cho, Cheongju-si, KR;

Jung Geun Kim, Seoul, KR;

Cheol MO Jeong, Icheon-si, KR;

Suk Joong Kim, Icheon-si, KR;

Jung Gu Lee, Seongnam-si, KR;

Inventors:

Cha Deok Dong, Icheon-si, KR;

Whee Won Cho, Cheongju-si, KR;

Jung Geun Kim, Seoul, KR;

Cheol Mo Jeong, Icheon-si, KR;

Suk Joong Kim, Icheon-si, KR;

Jung Gu Lee, Seongnam-si, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.


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