The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

Apr. 08, 2008
Applicants:

Tatsuo Inoue, Tokyo, JP;

Osamu Arai, Tochigi, JP;

Katsushi Mikuni, Aomori, JP;

Norihiro Imai, Aomori, JP;

Inventors:

Tatsuo Inoue, Tokyo, JP;

Osamu Arai, Tochigi, JP;

Katsushi Mikuni, Aomori, JP;

Norihiro Imai, Aomori, JP;

Assignee:

Kabushiki Kaisha Nihon Micronics, Musashino-shi, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H05K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is deposited on the flat surface. The multilayer wiring board comprises a multilayer wiring layer on whose surface convexo-concave is formed, a dummy layer burying the convexo-concave, a resistance material layer made of an electrical resistance material deposited on the dummy layer and at an area going beyond the dummy layer, and a wire made of a conductive material deposited on the resistance material layer and ranging from the area going beyond the dummy layer to a part of the flat surface area of the dummy layer, wherein a resistive element is formed at an area of the resistance material layer that the wire does not reach.


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