The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Aug. 03, 2006
Lior Amarilio, Yokneam, IL;
Yoav Segal, Modiin, IL;
Lior Amarilio, Yokneam, IL;
Yoav Segal, Modiin, IL;
ChipX, Inc., Santa Clara, CA (US);
Abstract
Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.