The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Jan. 19, 2007
Method for designing cell layout of a semiconductor integrated circuit with logic having a data flow
Katsuyuki Itoh, Hadano, JP;
Hironori Iwamoto, Hadano, JP;
Katsuyuki Itoh, Hadano, JP;
Hironori Iwamoto, Hadano, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. The present invention extracts cells of a specific type specified from outside or cells satisfying specific conditions, arranges these specific cells first or limits a layout position by specifying a layout position, then arranges the remaining cells using a general layout algorithm.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile