The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Sep. 18, 2007
Yoshinori Soejima, Fukuoka, JP;
Yoshikatsu Kouhara, Fukuoka, JP;
Hiroaki Shiraishi, Fukuoka, JP;
Kouichi Tanda, Fukuoka, JP;
Takakazu Tokunaga, Fukuoka, JP;
Koji Takatomi, Fukuoka, JP;
Yoshinori Soejima, Fukuoka, JP;
Yoshikatsu Kouhara, Fukuoka, JP;
Hiroaki Shiraishi, Fukuoka, JP;
Kouichi Tanda, Fukuoka, JP;
Takakazu Tokunaga, Fukuoka, JP;
Koji Takatomi, Fukuoka, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#).