The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Oct. 27, 2004
Phillip M. Hoffman, Oreland, PA (US);
Jessica A. Paragas, Springfield, PA (US);
Anthony P. Matyok, Springfield, PA (US);
Jeffery A. Stell, Exton, PA (US);
Sharon M. Mauer, West Chester, PA (US);
James W. Thompson, West Chester, PA (US);
Phillip M. Hoffman, Oreland, PA (US);
Jessica A. Paragas, Springfield, PA (US);
Anthony P. Matyok, Springfield, PA (US);
Jeffery A. Stell, Exton, PA (US);
Sharon M. Mauer, West Chester, PA (US);
James W. Thompson, West Chester, PA (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
A method and system for maintaining the execution speed of a multiprocessor computer system includes automatically detecting a change in instruction execution rate in a disabled processor by a threshold amount and determining an amount of change in instruction execution rate to adjust an actual system-level instruction execution rate to approximate a target system-level instruction execution rate. The target system-level execution rate being pre-determined. Thereafter, the method adjusts one or more instruction processor execution rates such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate to overcome the loss of the disabled processor. One embodiment of the invention involves the use of a processor key for licensing of processor resources within the computer system and offers the option of enabling a dynamic processor recovery method as well as an automatic execution rate regulation method.