The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2010

Filed:

Oct. 15, 2007
Applicants:

Hiroaki Nakano, Yokohama, JP;

Toshimasa Namekawa, Ota-ku, JP;

Hiroshi Ito, Yokohama, JP;

Osamu Wada, Yokohama, JP;

Atsushi Nakayama, Yokohama, JP;

Inventors:

Hiroaki Nakano, Yokohama, JP;

Toshimasa Namekawa, Ota-ku, JP;

Hiroshi Ito, Yokohama, JP;

Osamu Wada, Yokohama, JP;

Atsushi Nakayama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.


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