The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2010

Filed:

Jul. 17, 2008
Applicants:

Keunwoo Kim, Somers, NY (US);

Rajiv V. Joshi, Yorktown Heights, NY (US);

Vinod Ramadurai, South Burlington, VT (US);

Inventors:

Keunwoo Kim, Somers, NY (US);

Rajiv V. Joshi, Yorktown Heights, NY (US);

Vinod Ramadurai, South Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical 'one' can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.


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