The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Aug. 15, 2008
Applicant:
Chiaki Takano, Austin, TX (US);
Inventor:
Chiaki Takano, Austin, TX (US);
Assignee:
Sony Computer Entertainment Inc., Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
Takano, Chiaki. (2010). Method and apparatus for adaptive clock phase control for lsi power reduction (U.S. Patent No. 7733150). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7733150
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile