The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Jul. 14, 2008
Delay circuit of delay locked loop having single and dual delay lines and control method of the same
Applicants:
Hyun-woo Lee, Ichon, KR;
Won-joo Yun, Ichon, KR;
Inventors:
Hyun-Woo Lee, Ichon, KR;
Won-Joo Yun, Ichon, KR;
Assignee:
Hynix Semiconductor Inc., , KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract
A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.