Set and segr resistant delay cell and delay line for power-on reset circuit applications

Abstract

A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a simple inverter delay line. The delay line of the present invention uses the selective placement of capacitors throughout the delay line, one-sided current starving, and the incorporation of one-sided Schmitt trigger circuits. Performance of the delay line is substantially immune to SEGR events ('Single Event Gate Rupture') and SET events ('Single Event Transients'). Spurious signals produced by SEGR and SET events are quickly and substantially attenuated.