Self test circuit for a semiconductor intergrated circuit

Abstract

A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKBis held in flip-flop circuitsynchronously with checking clock signal A. Checking pattern signal PAT_A is held in flip-flop circuitsynchronously with checking clock signal A. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuitis input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuitis input instead of clock signal DA_IN. The timing relationship between clock signal CKBand checking timing signal Aand the timing relationship between clock signal CKBand checking timing signal Aare controlled independently by timing control circuit