The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2010

Filed:

Jan. 24, 2007
Applicant:

Jen-chieh Chen, Taipei, TW;

Inventor:

Jen-Chieh Chen, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.


Find Patent Forward Citations

Chen, Jen-Chieh. (2010). Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state (U.S. Patent No. 7730337). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7730337

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…