High-speed interface for a programmable device

Abstract

A high-speed interface for implementation in a programmable device such as, e.g., a programmable logic device ('PLD') is described. Multi-gigabit transceivers of the PLD provide transmit and receive lock signals and have inputs for reference transmit and receive clock signals. One of the multi-gigabit transceivers provides a first transmit clock signal, a first receive clock signal, and a second receive clock signal. A data rate converter fractionally multiplies a second transmit clock signal to provide the reference transmit clock signal. A skew synchronization block obtains respective transmit and receive lock signals from the multi-gigabit transceivers and provides respective receive and transmit synch adjustment signals to the multi-gigabit transceivers. Synchronous operation of the multi-gigabit transceivers in receive and transmit directions is adjusted with receive and transmit synch adjustment signals to maintain lane-to-lane skew for the high-speed interface within a target range.