The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Feb. 11, 2008
Anthony Gus Aipperspach, Rochester, MN (US);
Phil Christopher Felice Paone, Rochester, MN (US);
Brian Joy Reed, Rochester, MN (US);
David Edward Schmitt, Rochester, MN (US);
Gregory John Uhlmann, Rochester, MN (US);
Anthony Gus Aipperspach, Rochester, MN (US);
Phil Christopher Felice Paone, Rochester, MN (US);
Brian Joy Reed, Rochester, MN (US);
David Edward Schmitt, Rochester, MN (US);
Gregory John Uhlmann, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.