The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Jul. 31, 2007
Michael Bozich Calhoun, Roseville, CA (US);
Dennis Carr, Roseville, CA (US);
Ricardo Ernesto Espinoza-ibarra, San Diego, CA (US);
Teddy Lee, Roseville, CA (US);
Lidia Warnes, Roseville, CA (US);
Michael Bozich Calhoun, Roseville, CA (US);
Dennis Carr, Roseville, CA (US);
Ricardo Ernesto Espinoza-Ibarra, San Diego, CA (US);
Teddy Lee, Roseville, CA (US);
Lidia Warnes, Roseville, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch. The auxiliary slot section includes a notch for receiving the third latch when the third latch is in a disengaged position, a retention notch that restrains movement of the third latch when the third latch is in an engaged position, and a power and signaling section that includes power and signaling connections usable by one or more of the memory device planars.