The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Oct. 10, 2008
Kevin NG, Fremont, CA (US);
Zhinan Wei, San Jose, CA (US);
Wai-keung Peter Cheng, Union City, CA (US);
Allen Chang, Fremont, CA (US);
Kevin Ng, Fremont, CA (US);
Zhinan Wei, San Jose, CA (US);
Wai-Keung Peter Cheng, Union City, CA (US);
Allen Chang, Fremont, CA (US);
Alpha & Omega Semiconductor, Inc., Sunnyvale, CA (US);
Abstract
A current limiting load switch for bridging supply Vss and load with a reference voltage VRdynamically generated by a VR-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIO=Is/Ipower<<1. The sense FET high-side terminal is coupled to Vss through a sense resistor Rsense developing a sense voltage Vs=Is×Rsense. A current limiting amplifier with inputs connected to VRand Vs and output controlling FET pair closing a current limiting feedback loop. The VR-generator dynamically adjusts VRconcurrent and compensatory with an undesirable effect of changing RATIOcaused by the sense FET operational transition thus eliminating a transitional overshoot of Iload beyond Imax.