The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2010

Filed:

Oct. 09, 2006
Applicants:

Hare K. Verma, Cupertino, CA (US);

Ravi Sunkavalli, Milpitas, CA (US);

Sudip Nag, San Jose, CA (US);

Conrad Kong, San Jose, CA (US);

BO HU, San Jose, CA (US);

Chandra Mulpuri, San Jose, CA (US);

Ashok Vittal, Fremont, CA (US);

Inventors:

Hare K. Verma, Cupertino, CA (US);

Ravi Sunkavalli, Milpitas, CA (US);

Sudip Nag, San Jose, CA (US);

Conrad Kong, San Jose, CA (US);

Bo Hu, San Jose, CA (US);

Chandra Mulpuri, San Jose, CA (US);

Ashok Vittal, Fremont, CA (US);

Assignee:

Agate Logic, Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.


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