The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Jan. 09, 2008
Akimori Hayashi, Kanagawa, JP;
Akimori Hayashi, Kanagawa, JP;
NEC Electronics Corporation, Kawasaki, Kanagawa, JP;
Abstract
A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other. In each of the first and second wirings, a wire is provided between a connection point for the terminal in a first one of the semiconductor chips and a position of a root, a complete binary tree structure in which all leaves are at the same depth from the root is formed, connection points for the terminals in the rest of the semiconductor chips are positioned at the respective leaves, and the paths of wires respectively corresponding to branches at the same depth in the tree structure include vias and the lengths of the paths of wires including the lengths of the vias are equal to each other.