The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2010

Filed:

Jul. 27, 2006
Applicants:

Hisao Sato, Ichihara, JP;

Hitoshi Takeda, Ichihara, JP;

Inventors:

Hisao Sato, Ichihara, JP;

Hitoshi Takeda, Ichihara, JP;

Assignee:

Showa Denko K.K., Toyko, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An object of the present invention is to provide a method for producing a gallium nitride-based compound semiconductor multilayer structure useful for the production of a gallium nitride-based compound semiconductor light-emitting device which can ensure that the operating voltage is reduced, the light emission output is good and the light emission output is less changed due to aging. The inventive production method of a gallium nitride-based compound semiconductor multilayer structure comprises a substrate having thereon an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, the light-emitting layer being disposed between the n-type semiconductor layer and the p-type semiconductor layer, and the light-emitting layer having a multiple quantum well structure formed by alternately stacking a well layer and a barrier layer, wherein at least one well layer has a non-uniform thickness, at least a part of the barrier layer is grown at a higher temperature than the well layer, and the temperature difference between each growth temperature of the well layer, the barrier layer and the p-type semiconductor layer is adjusted to be in a specific range.


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