The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
May. 05, 2006
Thai Cheng Chua, Cupertino, CA (US);
Cory Czarnik, Saratoga, CA (US);
Andreas G. Hegedus, Burlingame, CA (US);
Christopher Sean Olsen, Fremont, CA (US);
Khaled Z. Ahmed, Anaheim, CA (US);
Philip Allan Kraus, San Jose, CA (US);
Thai Cheng Chua, Cupertino, CA (US);
Cory Czarnik, Saratoga, CA (US);
Andreas G. Hegedus, Burlingame, CA (US);
Christopher Sean Olsen, Fremont, CA (US);
Khaled Z. Ahmed, Anaheim, CA (US);
Philip Allan Kraus, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.