The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Feb. 27, 2007
Ernst Mayer, Cupertino, CA (US);
Ernst Mayer, Cupertino, CA (US);
Agate Logic, Inc., Cupertino, CA (US);
Abstract
The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a graph theoretic tree, mapping each target to a target node; mapping each driver to a driver node; and routing each driver and its targets as a function of the minimum spanning tree spanning each driver node and its target nodes by traversing from the target nodes of a driver backwards toward its driver node in said tree. The methods of this invention are straightforward to implement, of polynomial time complexity, and can optimize routing resource usage.