The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Aug. 08, 2006
Laurent Fabris Stadler, San Francisco, CA (US);
Laurent Fabris Stadler, San Francisco, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.