The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Aug. 30, 2002
Applicants:

Zhao Wu, San Jose, CA (US);

Heng Liao, Belcarra, CA;

Inventors:

Zhao Wu, San Jose, CA (US);

Heng Liao, Belcarra, CA;

Assignee:

PMC-Sierra, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04J 3/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.


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