Memory controller with programmable regression model for power control

Abstract

A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are blocked. A regression model bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors. In the illustrative implementation the operating factors include power consumption, a current number of bank conflicts, a current number of read commands, and a current number of write commands. Different sets of regression coefficients can be programmably stored for use with different system configurations.