The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Apr. 19, 2007
Vinson Chan, San Jose, CA (US);
Chong H. Lee, San Ramon, CA (US);
Binh Ton, San Jose, CA (US);
Thiagaraja Gopalsamy, San Jose, CA (US);
Marcel A. Leblanc, Sunnyvale, CA (US);
Neville Carvalho, Campbell, CA (US);
Vinson Chan, San Jose, CA (US);
Chong H. Lee, San Ramon, CA (US);
Binh Ton, San Jose, CA (US);
Thiagaraja Gopalsamy, San Jose, CA (US);
Marcel A. LeBlanc, Sunnyvale, CA (US);
Neville Carvalho, Campbell, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.