The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Jul. 24, 2007
Hiroshi Miyazaki, Kasugai, JP;
Hiroshi Miyazaki, Kasugai, JP;
Fujitsu Microelectronics Limited, Yokohama, JP;
Abstract
An output buffer circuit that suppresses the generation of an erroneous operation signal during power activation includes a first level converter generating a first signal based on a data input signal having an amplitude range between a first power supply potential and a ground reference potential. The first signal has an amplitude range between a second power supply potential, which differs from the first power supply potential, and the ground reference potential. A second level converter generates a second signal having an amplitude range between the second power supply and ground reference potentials based on a control input signal having an amplitude range between the first power supply and ground reference potentials. The first signal falls with a delay from the second signal. An output circuit generates an output signal. A timing adjustment circuit compensates for the fall delay of the first signal during power activation.