The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Oct. 31, 2007
Won Chon, Torrance, CA (US);
Nick J. Rosik, Redondo Beach, CA (US);
Harry H. Kim, Cerritos, CA (US);
Gregory D. Surbeck, Oxford, MS (US);
Gharib Gharibianians, Tustin, CA (US);
Dean W. Schoettler, Rancho Palos Verdes, CA (US);
Won Chon, Torrance, CA (US);
Nick J. Rosik, Redondo Beach, CA (US);
Harry H. Kim, Cerritos, CA (US);
Gregory D. Surbeck, Oxford, MS (US);
Gharib Gharibianians, Tustin, CA (US);
Dean W. Schoettler, Rancho Palos Verdes, CA (US);
Raytheon Company, Waltham, MA (US);
Abstract
An active clamp circuit for electronic components includes two sets of diode connected transistors that are inversely connected in parallel across an output of the component for providing both positive and negative differential conducting paths. The diode connected transistors cooperatively operate to limit a differential output voltage between the positive and negative conducting paths. An emitter follower buffer includes the clamp circuit and is configured to limit RF energy incident to an analog to digital converter (ADC). The emitter follower buffer includes two input transistors having their emitters each connected to at least one diode connected transistor connected to the clamp circuit. A receiver includes the differential amplifier and an analog to digital converter. A method for limiting the energy of analog signals in the receiver includes the step of operating the clamp circuit to limit the analog signals transmitted to the analog to digital converter (ADC).