The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Apr. 11, 2008
Ahmad R. Ansari, San Jose, CA (US);
Alex S. Warshofsky, Miami Beach, FL (US);
Ahmad R. Ansari, San Jose, CA (US);
Alex S. Warshofsky, Miami Beach, FL (US);
XILINX, Inc., San Jose, CA (US);
Abstract
An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.