The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Sep. 23, 2008
Moriyoshi Nakashima, Amagasaki, JP;
Kazuo Kobayashi, Amagasaki, JP;
Natsuo Ajika, Amagasaki, JP;
GENUSION, Inc., Hyogo, JP;
Abstract
A semiconductor chip mounted interposer () is configured by executing wire bonding between a semiconductor chip () and an interposer (), in which terminals () that connect to terminals () of the chip () and separate terminals () are formed, on the upper face of the interposer (). A semiconductor chip () is mounted to the top face of a package substrate (), the interposer () is adhered to the upper portion of the chip (), and wire bonding is executed between the terminals () and terminals ('). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.