The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Mar. 27, 2006
Applicants:

Vishnu K. Khemka, Chandler, AZ (US);

Amitava Bose, Tempe, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Ronghua Zhu, Chandler, AZ (US);

Inventors:

Vishnu K. Khemka, Chandler, AZ (US);

Amitava Bose, Tempe, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Ronghua Zhu, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench () formed therein. The isolation trench () may have first and second opposing inner walls () and a floor (). First and second conductive plates () may be formed over the first and second opposing inner walls () of the isolation trench () respectively such that there is a gap () between the first and second conductive plates (). First and second semiconductor devices () may be formed in the semiconductor substrate on opposing sides of the isolation trench (). The method may include forming a trench () in a semiconductor substrate, forming first and second conductive plates () within the trench, and forming first and second semiconductor devices () in the semiconductor substrate on opposing sides of the trench ().


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