The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Dec. 13, 2007
Applicants:

Eun-young Kang, Seoul, KR;

Jun Seo, Suwon-si, KR;

Jae-seung Hwang, Suwon-si, KR;

Sung-il Cho, Seoul, KR;

Yong-hyun Kwon, Hwaseong-si, KR;

Inventors:

Eun-young Kang, Seoul, KR;

Jun Seo, Suwon-si, KR;

Jae-seung Hwang, Suwon-si, KR;

Sung-il Cho, Seoul, KR;

Yong-hyun Kwon, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.


Find Patent Forward Citations

Loading…