The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2010

Filed:

May. 28, 2008
Applicants:

Saeed Azimi, Union City, CA (US);

Son Ho, Los Altos, CA (US);

Daniel Smathers, Boulder, CA (US);

Inventors:

Saeed Azimi, Union City, CA (US);

Son Ho, Los Altos, CA (US);

Daniel Smathers, Boulder, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.


Find Patent Forward Citations

Azimi, Saeed. (2010). Apparatus and method for testing and debugging an integrated circuit (U.S. Patent No. 7721167). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7721167

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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