The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 2010
Filed:
Aug. 24, 2006
Louis Bennie Capps, Jr., Georgetown, TX (US);
Warren D. Dyckman, Peekskill, NY (US);
Joanne Ferris, Essex, VT (US);
Anand Haridass, Austin, TX (US);
James Douglas Jordan, Round Rock, TX (US);
Ronald Edward Newhart, Essex Junction, VT (US);
Michael Richard Ouellette, Westford, VT (US);
Michael Jay Shapiro, Austin, TX (US);
Louis Bennie Capps, Jr., Georgetown, TX (US);
Warren D. Dyckman, Peekskill, NY (US);
Joanne Ferris, Essex, VT (US);
Anand Haridass, Austin, TX (US);
James Douglas Jordan, Round Rock, TX (US);
Ronald Edward Newhart, Essex Junction, VT (US);
Michael Richard Ouellette, Westford, VT (US);
Michael Jay Shapiro, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.