The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 2010
Filed:
Dec. 11, 2008
Arnaud Casagrande, Hauterive, CH;
Carlos Velasquez, Neuchâtel, CH;
Jean-luc Arend, Neuchâtel, CH;
The Swatch Group Research and Development Ltd., Marin, CH;
Abstract
The dual-modulus prescaler circuit () is devised to operate at a very high frequency. This circuit includes an assembly formed of two dynamic D-type flip flops (), and two NAND logic gates () arranged in negative feedback between the two flip flops. The two flip flops are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency matches the input clock frequency divided by 2 or by 3 as a function of a division mode selection signal (divb) applied to the input of the first NAND logic gate (). One non-inverted output of the second flip flop is connected to one input of the first flip flop (). The first dynamic flip flop includes three active branches and supplies a single inverted output signal. A third flip flop () with three active branches receives an inverted mode selection signal (div) at input in order to supply the mode selection signal to the inverted output thereof, clocked by the non-inverted output signal of the second flip flop.