The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 2010
Filed:
May. 26, 2004
Michael Edward Flatté, Iowa City, IA (US);
Zhi Gang Yu, Mountain View, CA (US);
Ezekiel Johnston-halperin, San Dimas, CA (US);
David Awschalom, Santa Barbara, CA (US);
Michael Edward Flatté, Iowa City, IA (US);
Zhi Gang Yu, Mountain View, CA (US);
Ezekiel Johnston-Halperin, San Dimas, CA (US);
David Awschalom, Santa Barbara, CA (US);
University of iowa Research Foundation, Iowa City, IA (US);
Abstract
A bipolar spin transistor is provided. In one embodiment of the present invention, the bipolar spin transistor includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type that is different from the first conductivity type and also having a spin polarization, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a first charge depletion layer therebetween, the first charge depletion layer having a first side facing the first semiconductor region and an opposing second side facing the second semiconductor region. Additionally, the second semiconductor region and the third semiconductor region are adjacent to each other so as to form a second charge depletion layer therebetween, the second charge depletion layer having a first side facing the second semiconductor region and an opposing second side facing the third semiconductor region.