The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Oct. 15, 2009
Tim Vanderhoek, Toronto, CA;
Vaughn Betz, Toronto, CA;
David Cashman, Toronto, CA;
David Lewis, Toronto, CA;
Michael Hutton, Mountain View, CA (US);
Tim Vanderhoek, Toronto, CA;
Vaughn Betz, Toronto, CA;
David Cashman, Toronto, CA;
David Lewis, Toronto, CA;
Michael Hutton, Mountain View, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device ('PLD') architecture includes logic elements ('LEs') grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.