Method and system for designing semiconductor circuit devices to reduce static power consumption

Abstract

A method and system are disclosed for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure. The method includes providing at least one library of cells with a variable channel length L; creating a layout of an integrated circuit using the cells with an initial channel length L; performing a timing analysis of the integrated circuit to analyze more and less critical paths by evaluating respective path delays; selecting a set of less critical paths to be modified; evaluating the leakage currents of the less critical paths of the selected set; and modifying the variable channel length L of the cells which are involved in the less critical paths of the selected set on the basis of the corresponding evaluated leakage current and the respective path delays, whereby a modified integrated circuit with a reduced circuit leakage current is obtained.