Method and apparatus to use clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator

Abstract

The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.