The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Jan. 31, 2007
Claude Basso, Raleigh, NC (US);
Jean L. Calvignac, Raleigh, NC (US);
Chih-jen Chang, Apex, NC (US);
Philippe Damon, Chapel Hill, NC (US);
Herman D. Dierks, Jr., Round Rock, TX (US);
Christoph Raisch, Gerlingen, DE;
Jan-bernd Themann, Tübingen, DE;
Natarajan Vaidhyanathan, Carrboro, NC (US);
Fabrice J. Verplanken, LaGaude, FR;
Colin B. Verrilli, Apex, NC (US);
Claude Basso, Raleigh, NC (US);
Jean L. Calvignac, Raleigh, NC (US);
Chih-jen Chang, Apex, NC (US);
Philippe Damon, Chapel Hill, NC (US);
Herman D. Dierks, Jr., Round Rock, TX (US);
Christoph Raisch, Gerlingen, DE;
Jan-Bernd Themann, Tübingen, DE;
Natarajan Vaidhyanathan, Carrboro, NC (US);
Fabrice J. Verplanken, LaGaude, FR;
Colin B. Verrilli, Apex, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.