Layout structure of semiconductor memory device having iosa

Abstract

Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed.