Phase locked loop circuit and wireless communication system

Abstract

In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.