The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2010

Filed:

Aug. 22, 2008
Applicants:

Johannes Gerber, Unterschleissheim, DE;

Vadim V. Ivanov, Tucson, AZ (US);

Ruediger Kuhn, Freising, DE;

Inventors:

Johannes Gerber, Unterschleissheim, DE;

Vadim V. Ivanov, Tucson, AZ (US);

Ruediger Kuhn, Freising, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01); G05F 3/16 (2006.01); G05F 3/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current.


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