The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Mar. 11, 2008
Chel Jong Choi, Daejeon, KR;
Moon Gyu Jang, Daejeon, KR;
Yark Yeon Kim, Daejeon, KR;
Myung Sim Jun, Daejeon, KR;
Tae Youb Kim, Seoul, KR;
Chel Jong Choi, Daejeon, KR;
Moon Gyu Jang, Daejeon, KR;
Yark Yeon Kim, Daejeon, KR;
Myung Sim Jun, Daejeon, KR;
Tae Youb Kim, Seoul, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.