The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2010

Filed:

Aug. 17, 2005
Applicants:

Nedim Fresko, San Francisco, CA (US);

Dean R. Long, Boulder Creek, CA (US);

Jiangli Zhou, San Jose, CA (US);

Inventors:

Nedim Fresko, San Francisco, CA (US);

Dean R. Long, Boulder Creek, CA (US);

Jiangli Zhou, San Jose, CA (US);

Assignee:

Oracle America, Inc., Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A trap-based mechanism is provided for gaining greater visibility into the memory usage of a process. To detect and record the memory accesses of a process, a virtual address range (or a plurality of address ranges) of the process is set to a protected status. This address range represents the range of virtual addresses that are to be monitored for access. By setting the address range to a protected status, whenever a memory access (in one implementation, whenever a memory write) is made to a virtual address within that address range, a trap arises. When the trap arises, a trap handler is invoked. When invoked, the trap handler records the virtual address that was accessed. In this manner, the access of the virtual address is detected and recorded without having to add extensive instrumentation code to the process.


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